UMVA has learned that a groundbreaking open-source silicon distribution called Pavona has been unveiled, promising to reshape how chip designers embed certification‑ready roots of trust and post‑quantum cryptography into everything from tiny IoT sensors to massive AI accelerators.
In today’s hyper‑connected world, the security foundation of a device is often set long before the first line of application code ever touches the silicon. For products expected to endure for years, that foundation—cryptographic accelerators, certification pathways, and immutable trust anchors—must be baked into the chip design itself.
Against this backdrop, Pavona arrives as a community‑governed toolkit that bundles secure IP blocks, a flexible composition engine, and reference top‑level designs. Its ambition stretches across a spectrum of architectures, from data‑center processors and automotive controllers to the most resource‑constrained embedded devices.
What truly sets Pavora apart is its distribution model. While many open‑silicon projects offer isolated cores or static reference chips, Pavona delivers a curated library of IP that can be mixed and matched, letting designers craft bespoke security subsystems tailored to their specific architecture instead of being forced into a one‑size‑fits‑all solution.
This modularity matters profoundly for IoT. A standalone secure element, an embedded root of trust inside a microcontroller, and a chiplet‑based trust anchor each pose distinct challenges. Pavona launches with two silicon‑proven reference designs—a standalone chip root of trust and an integrated chiplet‑compatible root—both fabricated at a leading 3 nm process, giving developers a concrete starting point beyond mere simulations.
According to information obtained by UMVA, the distribution aligns with the rigorous FIPS 140‑3 and Common Criteria certification frameworks. While this alignment does not grant automatic certification, it equips OEMs and semiconductor teams with an architecture primed for the certification journey, shifting the burden of validation and evidence collection to the implementer.
The cryptographic stack embedded in Pavona is equally revolutionary. It incorporates both classical algorithms and the newly standardized post‑quantum schemes ML‑KEM and ML‑DSA. Collaborative research from leading academia and industry demonstrated 6‑to‑9× performance gains for these algorithms on embedded silicon, alongside 36‑to‑75 % higher operating frequencies—all achieved with negligible area overhead.
For long‑lived devices—industrial controllers, utility meters, automotive electronics—the implication is clear: post‑quantum readiness can no longer be deferred to a software patch. By embedding efficient PQ‑C support at design‑time, Pavona gives chip makers a viable path to future‑proof security long before devices hit the market.
The initiative is stewarded by a diverse coalition of semiconductor innovators, research institutes, and standards bodies, operating under an open‑source governance model reminiscent of projects like Yocto and Zephyr. This broad backing ensures that secure silicon adoption is driven not just by IP availability but by a unified ecosystem of suppliers, software communities, and end‑product stakeholders.
For OEMs, Pavona lowers the barrier to experimenting with root‑of‑trust architectures without locking into proprietary, single‑vendor solutions. System integrators and industrial players stand to benefit from devices built on composable, certification‑aligned silicon, which can simplify assessment, attestation, and lifecycle management across heterogeneous deployments.
While Pavona does not erase the inherent complexities of secure hardware design—verification, certification, and long‑term support remain demanding—it marks a pivotal moment by converging open silicon, standards compliance, and post‑quantum readiness into a single, cohesive distribution.
